Verification Language: 3 points to ponder beyond "which one?"
Cadence introduces universal verification components
Cadence verification IP claims broad language support
XLX Solutions : Design Verification Products
An in depth analysis of verification methodology, technology selection, and the value of Verification IP.
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Welcome to the XLX Solutions Verification Newsletter. In this edition we bring you an exciting collection of articles and a ground breaking press release in the field of design verification. Enjoy! James Colgan
The discussion and debate around "e" and SystemVerilog continue, but are we missing the point? An interesting perspective from Globetech Solutions and Cadence with an active discussion on EDACafe.
First Verification-Plan-Enabled Verification IP Integrates Compliance Management and Mixed Language Support.
An EETimes report on Cadence multi-language support with their Universal Verification Component (UVC) strategy and products.
Design Verification Kits
Analog Mixed-Signal
DFT
Verification IP
ATAPI Host & Device eVCs
CAN 2.0b eVC
CE-ATA eVC
IEEE 1149.1 (JTAG) eVC
IEEE 1500 (SECT) eVC
LIN eVC
OCP 2.1 eVC
IrDA eVC
UART eVC
UART 16x50 eVC
