SAN FRANCISCO — Looking to expand the footprint of its vPlan, or verification plan, into the world of verification intellectual property (IP), EDA market leader Cadence Design Systems Inc. Monday (Aug. 7) introduced a new line of reusable verification IP said to integrate compliance management and mixed-language flexibility with advanced simulation-based testbench technology.

According to Cadence (San Jose, Calif.), Universal Verification Components (UVCs) maximize quality, predictability and efficiency, while minimizing schedule delay risks and the need for specific protocol expertise. UVCs are part of Cadence's strategy to deliver verification IP that spans the entire verification process, the company said.

UVCs are intended to help alleviate the verification bottleneck in IP, Steve Glaser, corporate vice president of marketing for Cadence's verification division, told EE Times. While it is often noted that 70 percent of design time is now being spent in verification, less attention is paid to the problem of IP verification, which is just as pervasive, Glaser said.

"Seventy percent of the design task has been consumed in verification," Glaser said. "And 70 percent of the IP issue is about verification IP, not just design IP."

Verification IP, like everything else about leading-edge design, has grown much more complex, said Glaser, who added that the issue applies not only to commercially available IP from vendors, but also internally developed verification IP within customers' design and verification functions.

"It's really all about verification, and there are so many different complex protocols that you need to verify against," Glaser said.

Cadence's component IP includes an executable verification plan that drives management of the verification process and automatically calibrates, measures and reports on protocol compliance, Cadence said. The company claims that UVCs are the industry's only verification IP to support all standard languages backed by the IEEE, including SystemVerilog and "e" for test benches, and SystemC, VHDL and SystemVerilog for design.

UVS also support reusability across all phases of design and verification and Cadence's plan to closure methodology, according to Peter Heller, product line Cadence product line manager for verification IP. Cadence said it would provide UVCs for the protocols most in demand by customers, including ARM's AMBA AHB and AXI, PCI Express, Ethernet and USB.

Each UVC is pre-verified against the protocol specifications and is based on Cadence's plan-to-closure methodology for plug-and-play adoption, according to the company. UVCs are already in customer use, Cadence said, and will become more broadly available this quarter.